Information processing apparatus

ABSTRACT

Provided is an information processing apparatus which can perform memory accesses from plural processing sections without breaking the memory accesses.  
     The information processing apparatus ( 101 ) is provided with the pre-stage processing section ( 3 ) which arbitrates among plural access requests with respect to the integrated memory ( 5 ) in the access request control circuit ( 22 ) and issues a predetermined number of access requests, the post-stage processing section ( 4 ) which issues plural access requests with respect to the integrated memory ( 5 ), and the integrated memory control circuit ( 18 ) which arbitrates among access requests from the pre-stage processing section ( 3 ) and the post-stage processing section ( 4 ), and outputs any of the access requests to the integrated memory ( 5 ), wherein the access request control circuit ( 22 ) and the integrated memory control circuit ( 18 ) are adapted to perform arbitration on the basis of the perioridicity of the respective access factors and the regularity of the access destination addresses.

TECHNICAL FIELD

The present invention relates to an information processing apparatus,and, more particularly, to an information processing apparatus which canperform memory accesses to one storage unit from plural processingsections without breaking the memory accesses.

BACKGROUND ART

Conventionally, as an information processing apparatus for accessing amedia in which data are accumulated, an information processing apparatuscomprising a pre-stage processing section which performs access to themedia such as reading and writing and a post-stage processing sectionwhich decodes and encodes data handled by the pre-stage processingsection and the like, is employed.

Hereinafter, a prior art information processing apparatus comprising thepre-stage processing section and the post-stage processing section willbe described with reference to the drawings. FIG. 6 is a block diagramillustrating a configuration of the prior art information processingapparatus 104.

The information processing apparatus 104 processes data accumulated inthe media 2, and comprises a pre-stage processing section 3 foraccessing the media 2, a post-stage processing section 4 for performingprocessing of data which are read from the media 2 by the pre-stageprocessing section 3 and creating data to be written into the media 2 bythe pre-stage processing section 3, a first memory 5 a which can beaccessed by the pre-stage processing section 3, and a second memory 5 bwhich can be accessed by the post-stage processing section 4. Thepre-stage processing section 3, the post-stage processing section 4, thefirst memory 5 a, and the second memory 5 b are semiconductor integratedcircuits, respectively, which are different from each other.

The pre-stage processing section 3 is connected to the media 2 through adata signal 6 a and a data signal 6 b, and has functions of either/bothreading data from the media 2 or/and writing data into the media 2. Inorder to realize the functions, the pre-stage processing section 3includes a requester group 401 as factors for generating plural accessrequests with respect to the first memory 5 a, and the requester group401 issues plural access requests through request signals 402 which areprovided by the same number as the number of access requests. Further,the pre-stage processing section 3 includes a memory control circuit 18a which arbitrates among plural access requests from the requester group401 to output one of the access requests to the first memory 5 a. Thememory control circuit 18 a is connected to the requester group 401through request signals 402 and a data signal 403 and to the firstmemory 5 a through a data signal 16.

The post-stage processing section 4 is connected to the pre-stageprocessing section 3 through a data signal 11 a and a data signal 11 b,and has functions of either/both performing processing of data which areread from the media 2 by the pre-stage processing section 3 or/andcreating data to be written into the media 2 by the pre-stage processingsection 3. Further, the post-stage processing section 4 includes arequester group 9 as factors for generating plural access requests withrespect to the second memory 5 b, and the requester group 9 issuesplural access requests through request signals 13 a which are providedby the same number as the number of access requests. Further, thepost-stage processing section 4 includes a memory control circuit 18 bwhich arbitrates among plural access requests from the requester group 9to output one of the access requests to the second memory 5 b. Thememory control circuit 18 b is connected to the requester group 9through request signals 13 a and a data signal 15 a and to the secondmemory 5 b through a data signal 17.

Here, the pre-stage processing section 3 performs media access such asreading and writing, while the post-stage processing section 4 performscomplicated processing such as decoding and encoding signals. Therefore,the post-stage processing section 4 performs more stages of processingthan the pre-stage processing section 3. In order to maintain datatransfer rates equally between the pre-stage processing section 3 andthe post-stage processing section 4, the first memory 5 a may be alow-speed DRAM (Dynamic Random Access Memory) and the second memory 5 bmay be an SDRAM (Synchronous Dynamic Random Access Memory) which canperform higher-speed processing than the first memory 5 a.

Next, an operation of the information processing apparatus 104constructed as above will be described. Here, a case where theinformation processing apparatus 104 is an apparatus which readscompressed data of video and audio which are recorded in a digitalversatile disk (hereinafter, referred to as a DVD), and outputs a videosignal and an audio signal, wherein the pre-stage processing section 3reads the compressed data from the DVD and the post-stage processingsection 4 restores the compressed data, will be taken as an example.

In a case where the information processing apparatus 104 is an apparatuswhich reads data recorded in the DVD and outputs a video signal and anaudio signal, the requester group 401 comprises the following accessfactors. That is, they are an access request from a central processingunit (not shown) which controls the information processing apparatus 104(hereinafter, referred to as a CPU request), a write access request fordemodulating data read from the media 2 and writing the demodulated datainto the first memory 5 a (hereinafter, referred to as ademodu-request), a read request for performing error correction of datawhich have been written by the demodu-request (hereinafter, referred toas an ECC read request), a correction request for error data found inthe error correction (hereinafter, referred to as an ECC correctionrequest), a read request for checking whether an error is left on theerror-corrected data or not (hereinafter, referred to as an EDCrequest), a read request for outputting data which is confirmed ashaving no error to the data signal 11 a (hereinafter, referred to as aHOST transfer request). The first memory 5 a to be accessed is a DRAM,and therefore each of these access factors is of one word length.

The respective access factors will be described in detail.

The CPU request is an access which influences control of the pre-stageprocessing section 3 and the whole information processing apparatus 104,and it is an access request of greater importance. Further, an accessdestination addresses are generated at random.

The access requests other than the CPU request are based on datastructure which is used at the error correction of DVD. An example ofthe data structure which is used at the error correction of DVD is shownin FIG. 7. In FIG. 7, D1 is a data area into which main data to betransmitted to the post-stage processing section 4 are stored, and C1 toC3 are redundant areas used for the error correction, respectively. Thedata area D1 has a capacity of e word length×g lines, and an address pdis given at the head thereof. Further, the redundant area C1 has acapacity of f word length×g lines and an address p1 is given at the headthereof, the redundant area C2 has a capacity of e word length×h linesand an address p2 is given at the head thereof, and the redundant areaC3 has a capacity of f word length×h lines and an address p3 is given atthe head thereof.

The demodu-request is a transfer request for developing data read fromthe media 2 into data structure shown in FIG. 7 and writing the data onthe memory. For the demodu-request, accessing is performed as shown inFIG. 8, and the access destination addresses consecutively change tosuch as pd, pd+1, pd+2, . . . . Further, since data are read from themedia 2 at low speed, once an access request is generated, a given timeinterval occurs until the subsequent access request is generated.However, when waiting time which exceeds this given time interval isgenerated before the demodu-request is accepted, some data which areread from the media 2 remain unprocessed, and thereby it is necessarythat the waiting time should be short.

The ECC read request requires that the data on the first memory 5 a beread so as to perform the error correction of the demodulated data. As amethod for reading data, there are two kinds of methods, i.e., anexternal code reading and an internal code reading. In the external codereading, the access destination addresses change as shown in FIG. 9.That is, a request for reading data of addresses pd, pd+n, pd+2n (n is anatural number), pd+3n is generated. For the ECC read request of theexternal code reading, a subsequent access request is generatedimmediately after a request is accomplished until the completion ofreading one vertical line. On the other hand, in the internal codereading, data are read in order similar to that for the demodu-request.Further, as in the external code reading, a subsequent access request isgenerated immediately after a request is accomplished until thecompletion of reading one horizontal line. For this ECC read request, asubsequent request is generated immediately after a request isaccomplished until completing a given process unit, and thereforeintensive execution is possible and there is resistance to waiting time.

In a case where an error is found in the data on the memory by anarithmetic (error correction) using data read by the ECC read request,an ECC correction request is issued. The access destination addressesfor the ECC correction request are generated at random, and an access ofa maximum of 16 bytes per one vertical line occurs in the correction ofthe external code reading, and an access of a maximum of 10 bytes perone horizontal line occurs in the correction of the internal codereading. The access requests are repetitions of 1 byte reading and 1byte writing. For the ECC correction request, once access requests arecontinuously issued by the number of errors which can be corrected, anaccess request is not issued until the completion of reading onevertical line for a subsequent ECC read request.

Both the EDC request and the HOST transfer request are requests forreading only data area D1. That is, the EDC request is one whichrequires that data be read so as to check whether an error is left onthe error-corrected data, while the HOST transfer request is one whichrequires that data which is confirmed as having no error be read andoutputted to the post-stage processing section 4 through the data signal11 a. The access destination addresses for these access requestsconsecutively change to such as pd, pd+1, pd+2 . . . . Further, asubsequent access request is generated immediately after a request isaccomplished until the whole data on the data area D1 are read. For theEDC request and HOST transfer request, a subsequent request is generatedimmediately after a request is accomplished until completing a givenprocess unit, and therefore intensive execution is possible and there isresistance to waiting time.

The priority arbitrated by the memory control circuit 18 a for theaccess requests issued by these access factors will be described.

In the pre-stage processing section 3, when an access to the firstmemory is generated in the process of reading data from the media 2 andwriting data into the media 2, the requester group 401 issues an accessrequest and the memory control circuit 18 a outputs the access requestto the first memory 5 a. In a case where plural access requests areissued from the requester group 401, the memory control circuit 18 aoutputs one of the access requests to the first memory 5 a on the basisof the priorities which are set according to the access factors.

In the post-stage processing section 4, when an access to the secondmemory 5 b is generated in the process of processing data supplied fromthe pre-stage processing section 3 and creating data to be written intothe media 2, the requester group 9 issues an request for accessing thesecond memory 5 b, to the memory control circuit 18 b. Since the secondmemory 5 b is an SDRAM, the requester group 9 issues a transfer requestof consecutive longer transfer length such as 32 word length and 64 wordlength.

An operation of the post-stage processing section 4 whose requestergroup 9 has three access factors of access factor A, access factor B,and access factor C in descending order of priority will be describedwith reference to FIG. 10. FIG. 10 shows access states for accessfactors A to C with assuming N=10 as a value of a natural number N whichis used in the following description. In FIG. 10, a location where “req”is described designates a time at which an access request is issued, anarea where “access” is described designates a time period during whichdata transfer is being performed, and an area where “wait” is describeddesignates a waiting time.

For the access factor A, an access request for occupying the secondmemory 5 b during 20N (N is a natural number) cycles inclusive ofoverhead for each access and an access request for occupying the secondmemory 5 b during 10N cycles inclusive of overhead for each access arealternately issued twice, and when four access requests areaccomplished, a suspension period of 200N cycles is entered. 8N cyclesare required from the accomplishment of an access request to theissuance of the subsequent access request. Further, for each of theaccess factor B and access factor C, an access request for occupying thesecond memory 5 b during 20N cycles inclusive of overhead for eachaccess is issued. For the access factor B, a new access request isissued after 20N cycles from the accomplishment of an access request,and for the access factor C, a new access request is issued after 30Ncycles from the accomplishment of an access request. These accessfactors are accomplished without generating long waiting time.

However, on a request of reduction in system cost and reduction infootprint, it is desired that the above-described pre-stage processingsection 3 and the post-stage processing section 4 be formed in a singleintegrated circuit and the memories which are individually included inthe pre-stage processing section 3 and the post-stage processing section4 be integrated into one shared memory.

FIG. 11 shows a configuration of an information processing apparatus 105in which the pre-stage processing section 3 and the post-stageprocessing section 4 are formed in a single integrated circuit and thefirst memory 5 a and the second memory 5 b are integrated into anintegrated memory 5. In FIG. 11, the same reference numerals as thoseshown in FIG. 1 denote the same or corresponding portions, and adetailed description will be omitted.

The integrated memory 5 may be an SDRAM like the second memory 5 b so asnot to reduce the processing speed of the post-stage processing section4. The integrated memory control circuit 18 is obtained by adding onechannel for accepting an access request to the memory control circuit 18b included in the post-stage processing section 4 in the informationprocessing apparatus 104, and a request signal 20 is connected to theadded channel so that an access request issued from the memory controlcircuit 18 a is input to the added channel. Further, the integratedmemory control circuit 18 is connected to the memory control circuit 18a through a data signal 21.

In the information processing apparatus 105 so constructed, when anaccess to the integrated memory 5 is generated, the pre-stage processingsection 3 issues access requests from the requester group 401, and thememory control circuit 18 a outputs one of the access requests to theintegrated memory control circuit 18 on the basis of the prioritieswhich are set according to the access factors. On the other hand, whenan access to the integrated memory 5 is generated, the post-stageprocessing section 4 issues requests for accessing the integrated memory5 from the requester group 9 to the integrated memory control circuit18. The integrated memory 5 arbitrates among the access request from thememory control circuit 18 a and the access requests from the requestergroup 9, and performs the request for accessing the integrated memory 5.

As described above, in the information processing apparatus 105, thememory integration can be accomplished only by adding one channel foraccepting an access request, to the memory control circuit 18 b of theinformation processing apparatus 104.

On the other hand, the following discussion is provided from a point ofview of a bandwidth. In a case where the integrated memory 5 is agenerally used SDRAM of 16 bit width, and the post-stage processingsection 4 operates this SDRAM at approximately 120 MHz, and thebandwidth of approximately 171 MB per second, which correspond toapproximately 75% of the whole bandwidth at worst inclusive of overheaddue to page miss, is occupied, the memory accesses for the followingquantities are required for the access factors from the requester group401, respectively, so that the pre-stage processing section 3 canperform DVD reading corresponding to double speed. 3.1 MB per second isrequired for the demodu-request from the requester group 401,approximately 9.3 MB per second is required for the ECC read requestwhen the number of times of error correction is three, approximately 0.6MB per second is required for the error correction request,approximately 2.7 MB per second is required for the EDC request, andapproximately 2.7 bytes per second is required for the HOST transferrequest. Therefore, the memory access should be accomplished at a rateof approximately 18.6 MB per second.

However, the memory control circuit 18 b issues an access request inunits of 1 to 4 bytes, and therefore there is a possibility thatoverhead due to page miss occurs extremely frequently. Considering theoccupied bandwidth for the post-stage processing section 4, the occupiedbandwidth for the pre-stage processing section 3 should be restricted toapproximately 57 MB per second. However, under the worst condition thatthe pre-stage processing section 3 always accesses the integrated memory5 in units of one word length, and overhead due to page miss occursevery time, the occupied bandwidth for the pre-stage processing section3 exceeds 57 MB per second, thereby breaking the bandwidth. A portion ofthe access requests generated by the access factors from the requestergroup 401 should be converted into the access requests of approximately30 to 40 word length so as to suppress the increase in pagemiss/overhead due to these access requests of shorter word lengths beingoverissued.

Further, while the requester group 9 in the post-stage processingsection 4 issues the access requests of 32 word length and 64 wordlength as described above, the CPU request and demodu-request issued bythe requester group 401 have greater importance and do not have room forwaiting time. Therefore, in a case where the CPU request anddemodu-request are caused to wait by the access requests generated byplural access factors from the requester group 9, there is a possibilitythat the memory access can not be completed within a required timeperiod. Therefore, the request signals 402 require a higher prioritythan all the access requests from the requester group 9 in the accessarbitration by the integrated memory control circuit 18. With this,however, the access requests such as the EDC request and HOST transferrequest are accepted at the higher priority. For these access factors,access requests are continuously issued until a given unit of processingis completed as described above, and therefore when these accessrequests are given the higher priority, the accesses from the requestergroup 9 are prevented, thereby substantially delaying the processing.

Here, the access states for the HOST transfer request, the EDC request,the ECC read request and the access factors A to C for a case where thepost-stage processing section 4 in the information processing apparatus105 has, as access factors, access factors A to C which are similar tothose of the information processing apparatus 104, will be describedwith reference to FIG. 12. FIG. 12 is a diagram illustrating the accessstates for the HOST transfer request, the EDC request, the ECC readrequest, and the access factors A to C.

It is necessary that the access requests generated by the access factorsfrom the requester group 401 should be converted into access requests oflonger word lengths so as to suppress increase in page miss/overhead dueto the access requests of shorter word lengths being overissued.Hereinafter, an access request obtained by converting an EDC requestinto an access request of longer word length is referred to as aconverted EDC request, an access request obtained by converting a HOSTtransfer request into an access request of longer word length isreferred to as a converted HOST transfer request, and an access requestobtained by converting an ECC read request into an access request oflonger word length is referred to as a converted ECC read request.

For each of the converted EDC request and the converted HOST request, anaccess request for occupying the SDRAM during 8N cycles inclusive ofoverhead is issued. For the converted ECC read request, an accessrequest for occupying the SDRAM during 10N cycles is continuously issuedand a suspension period of 200N cycles is entered. For the converted EDCrequest, 20N cycles are required from the accomplishment of a requestuntil a subsequent converted EDC access request can be issued. For theconverted HOST transfer request, 24N cycles are required from theaccomplishment of a request until a subsequent converted HOST transferrequest can be issued. Further, the memory control circuit 18 aarbitrates among plural access requests of the pre-stage processingsection 3 to output an access request to the integrated memory controlcircuit 18. In such a memory access state, as shown in FIG. 12, theaccess factor C of the post-stage processing section 4 is forced to havean abnormally longer waiting time, thereby breaking micro memory accessand completely delaying the accesses.

The present invention is made to solve the above-mentioned problems andits object is to provide an information processing apparatus whichsuppresses overissue of the access requests of shorter word lengths andcan perform memory accesses from plural processing sections withoutbreaking bandwidth due to overhead caused by page miss.

DISCLOSURE OF THE INVENTION

In order to solve the above-mentioned problems, an informationprocessing apparatus according to claim 1 of the present inventioncomprises: a storage unit for storing data; a first data processingsection for issuing plural access requests and accessing the storageunit; a second data processing section for issuing access requests andaccessing the storage unit; an access request controller for arbitratingamong the plural access requests of the first data processing section tooutput a predetermined number of access requests; and an accessarbitration unit for arbitrating among the access requests from theaccess request controller and the access requests from the second dataprocessing section.

According to claim 2 of the present invention, there is provided theinformation processing apparatus as defined in claim 1 wherein theaccess request controller comprises an arbitration unit which adds ahigher priority or a lower priority than a priority for the accessrequests of the second data processing section, to the access requestsfrom the first data processing section to issue the access requests.

According to claim 3 of the present invention, there is provided theinformation processing apparatus as defined in claim 2 wherein the firstdata processing section comprises: a first access request generationunit for generating access requests of a higher priority; and a secondaccess request generation unit for generating access requests having alower priority and consecutiveness in the access destination address,wherein the arbitration unit issues the access requests from the firstaccess request generation unit at the highest priority and issues theaccess requests from the second access request generation unit at apriority lower than that of the access requests from the second dataprocessing section.

According to claim 4 of the present invention, there is provided theinformation processing apparatus as defined in claim 2, wherein theaccess request controller comprises a buffer for accumulating data, andwhen an access request from the first data processing section is a writerequest with respect to the storage unit, the arbitration unit judgeswhether the arbitration unit issues an access request for writing a dataamount which is requested by the write request, or accumulates aspecified amount of data to be written, in the buffer, and thereafterconverts the request into an access request for intensively writing theaccumulated data to issue the converted access request.

According to claim 5 of the present invention, there is provided theinformation processing apparatus as defined in claim 2 wherein theaccess request controller comprises a buffer for accumulating data, andwhen an access request from the first data processing section is a readrequest with respect to the storage unit, the arbitration unit judgeswhether the arbitration unit issues an access request for reading dataof an amount requested by the read request, or converts the request intoan access request for intensively and previously reading more data thanthe requested amount by a specified amount and accumulating the readdata in the buffer to issue the converted access request, or reads thedata accumulated in the buffer without issuing an access request.

According to claim 6 of the present invention, there is provided theinformation processing apparatus as defined in claim 2 wherein when anaccess request from the first data processing section is periodicallygenerated at regular time intervals, the arbitration unit issues theaccess request at a priority higher than that of access requests fromthe second data processing section, and when an access request from thefirst data processing section is continuously generated with no timeinterval after an access request is accomplished, the arbitration unitissues the access request at a priority lower than that of accessrequests from the second data processing section.

According to claim 7 of the present invention, there is provided theinformation processing apparatus as defined in any of claims 1 to 6wherein the first data processing section comprises: a demodulating andwriting means for demodulating data recorded in a storage medium whichcan be accessed by the first data processing section and writing thedemodulated data into the storage unit; an error correction means forreading data written in the storage unit and writing error-correcteddata obtained by error-correcting the read data into the storage unit;an error detection means for reading the data which have beenerror-corrected from the storage unit and checking the data for error;and a reading means for reading data which is confirmed as having noerror by the error detection means, from the storage unit, andoutputting the read data to the second data processing section, and whenan access request from the first data processing section is generated bythe demodulating and writing means, the arbitration unit sets a priorityfor an access request to be issued to the access arbitration unit to behigher than a priority for access requests from the second dataprocessing section, and when an access request from the first dataprocessing section is generated by any of the error correction means,the error detection means, and the reading means, the arbitration unitsets a priority for an access request to be issued to the accessarbitration unit to be lower than a priority for access requests fromthe second data processing section.

According to claim 8 of the present invention, there is provided theinformation processing apparatus as defined in claim 1 wherein thesecond data processing section or the access arbitration unit comprisesan access frequency detection unit for detecting a time period duringwhich occurrence frequency of access to the storage unit from the seconddata processing section is low, and notifying the access requestcontroller of the time period, and the access request controllersuppresses issuance of access requests except in the time period andpromotes issuance of access requests in the time period on the basis ofthe notification from the access frequency detection unit.

According to claim 9 of the present invention, there is provided theinformation processing apparatus as defined in claim 1 wherein the firstdata processing section comprises: an error correction means for readingdata written in the storage unit and writing error-corrected dataobtained by error-correcting the read data into the storage unit; and areading means for reading data which is confirmed as having no error bythe error detection means, from the storage unit, and outputting theread data to the second data processing section, and the second dataprocessing section or the access arbitration unit comprises an accessfrequency detection unit for detecting a start and an end of a timeperiod during which occurrence frequency of access to the storage unitfrom the second data processing section is low, and notifying the accessrequest controller of the start and the end, and the first dataprocessing section operates the error correction means and the readingmeans when the start of the time period is detected by the accessfrequency detection unit, and the first data processing section delaysor stops the operations of the error correction means and the readingmeans when the end of the time period is detected.

As described above, an information processing apparatus according toclaim 1 of the present invention comprises: a storage unit for storingdata; a first data processing section for issuing plural access requestsand accessing the storage unit; a second data processing section forissuing access requests and accessing the storage unit; an accessrequest controller for arbitrating among the plural access requests ofthe first data processing section to output a predetermined number ofaccess requests; and an access arbitration unit for arbitrating amongthe access requests from the access request controller and the accessrequests from the second data processing section. Therefore, even whenthe processing speed of the first data processing section is low and thesecond data processing section requires high-speed processing, the firstand the second processing sections can share the storage unit withoutbreaking memory accesses. With this, a low-speed storage unit which isconventionally required so as to be accessed by the first dataprocessing section is dispensed with, and further the first dataprocessing section and the second data processing section can be formedin a single semiconductor integrated circuit, thereby reducing thenumber of components and a footprint of the information processingapparatus and reducing production cost.

According to claim 2 of the present invention, there is provided theinformation processing apparatus as defined in claim 1 wherein theaccess request controller comprises an arbitration unit which adds ahigher priority or a lower priority than a priority for the accessrequests of the second data processing section, to the access requestsfrom the first data processing section to issue the access requests.Therefore, an arbitration is performed on the basis of the priorities ofthe respective access requests, thereby avoiding breakage of memoryaccesses.

According to claim 3 of the present invention, there is provided theinformation processing apparatus as defined in claim 2 wherein the firstdata processing section comprises: a first access request generationunit for generating access requests of a higher priority; and a secondaccess request generation unit for generating access requests having alower priority and consecutiveness in the access destination address,wherein the arbitration unit issues the access requests from the firstaccess request generation unit at the highest priority and issues theaccess requests from the second access request generation unit at apriority lower than that of the access requests from the second dataprocessing section. Therefore, an arbitration is performed on the basisof the priorities of the respective access requests, thereby avoidingbreakage of memory accesses.

According to claim 4 of the present invention, there is provided theinformation processing apparatus as defined in claim 2 wherein theaccess request controller comprises a buffer for accumulating data, andwhen an access request from the first data processing section is a writerequest with respect to the storage unit, the arbitration unit judgeswhether the arbitration unit issues an access request for writing a dataamount which is requested by the write request, or accumulates aspecified amount of data to be written, in the buffer, and thereafterconverts the request into an access request for intensively writing theaccumulated data to issue the converted access request. Therefore,priorities of the respective access requests can be judged based onwhether the regularity of the access destination address is present ornot.

According to claim 5 of the present invention, there is provided theinformation processing apparatus as defined in claim 2 wherein theaccess request controller comprises a buffer for accumulating data, andwhen an access request from the first data processing section is a readrequest with respect to the storage unit, the arbitration unit judgeswhether the arbitration unit issues an access request for reading dataof an amount requested by the read request, or converts the request intoan access request for intensively and previously reading more data thanthe requested amount by a specified amount and accumulating the readdata in the buffer to issue the converted access request, or reads thedata accumulated in the buffer without issuing an access request.Therefore, priorities of the respective access requests can be judgedbased on whether the regularity of the access destination address ispresent or not, and further when data are accumulated in the buffer, thedata are read from the buffer, thereby reducing accesses to the storageunit.

According to claim 6 of the present invention, there is provided theinformation processing apparatus as defined in claim 2 wherein when anaccess request from the first data processing section is periodicallygenerated at regular time intervals, the arbitration unit issues theaccess request at a priority higher than that of access requests fromthe second data processing section, and when an access request from thefirst data processing section is continuously generated with no timeinterval after an access request is accomplished, the arbitration unitissues the access request at a priority lower than that of accessrequests from the second data processing section. Therefore, prioritiesof the respective access requests can be judged based on whether theperiodicity of the regularity in occurrence of an access factor ispresent or not.

According to claim 7 of the present invention, there is provided theinformation processing apparatus as defined in any of claims 1 to 6wherein the first data processing section comprises: a demodulating andwriting means for demodulating data recorded in a storage medium whichcan be accessed by the first data processing section and writing thedemodulated data into the storage unit; an error correction means forreading data written in the storage unit and writing error-correcteddata obtained by error-correcting the read data into the storage unit;an error detection means for reading the data which have beenerror-corrected from the storage unit and checking the data for error;and a reading means for reading data which is confirmed as having noerror by the error detection means, from the storage unit, andoutputting the read data to the second data processing section, and whenan access request from the first data processing section is generated bythe demodulating and writing means, the arbitration unit sets a priorityfor an access request to be issued to the access arbitration unit to behigher than a priority for access requests from the second dataprocessing section, and when an access request from the first dataprocessing section is generated by any of the error correction means,the error detection means, and the reading means, the arbitration unitsets a priority for an access request to be issued to the accessarbitration unit to be lower than a priority for access requests fromthe second data processing section. Therefore, priorities of therespective access requests can be judged on the basis of the kinds ofaccess factors.

According to claim 8 of the present invention, there is provided theinformation processing apparatus as defined in claim 1 wherein thesecond data processing section or the access arbitration unit comprisesan access frequency detection unit for detecting a time period duringwhich occurrence frequency of access to the storage unit from the seconddata processing section is low, and notifying the access requestcontroller of the time period, and the access request controllersuppresses issuance of access requests except in the time period andpromotes issuance of access requests in the time period on the basis ofthe notification from the access frequency detection unit. Therefore,the issuance frequency of access requests from the first data processingsection can be controlled on the basis of the occurrence frequency ofaccesses from the second data processing section, thereby suppressingbreakage of memory accesses.

According to claim 9 of the present invention, there is provided theinformation processing apparatus as defined in claim 1 wherein the firstdata processing section comprises: an error correction means for readingdata written in the storage unit and writing error-corrected dataobtained by error-correcting the read data into the storage unit; and areading means for reading data which is confirmed as having no error bythe error detection means, from the storage unit, and outputting theread data to the second data processing section, and the second dataprocessing section or the access arbitration unit comprises an accessfrequency detection unit for detecting a start and an end of a timeperiod during which occurrence frequency of access to the storage unitfrom the second data processing section is low, and notifying the accessrequest controller of the start and the end, and the first dataprocessing section operates the error correction means and the readingmeans when the start of the time period is detected by the accessfrequency detection unit, and the first data processing section delaysor stops the operations of the error correction means and the readingmeans when the end of the time period is detected. Therefore, theissuance frequency of access requests generated by the error correctionmeans and the reading means in the first data processing section can becontrolled on the basis of the occurrence frequency of accesses from thesecond data processing section, thereby suppressing breakage of memoryaccesses.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a configuration (a) of aninformation processing apparatus and a configuration (b) of an accessrequest control circuit according to a first embodiment of the presentinvention.

FIG. 2 is a diagram illustrating an access state of the pre-stageprocessing section in the information processing apparatus according tothe first embodiment of the present invention.

FIG. 3 is a diagram illustrating an access state of the pre-stageprocessing section and a post-stage processing section in theinformation processing apparatus according to the first embodiment ofthe present invention.

FIG. 4 is a block diagram illustrating a configuration (a) of aninformation processing apparatus and a configuration (b) of an accessrequest control circuit according to a second embodiment of the presentinvention.

FIG. 5 is a block diagram illustrating a configuration of an informationprocessing apparatus according to a third embodiment of the presentinvention.

FIG. 6 is a block diagram illustrating a configuration of a prior artinformation processing apparatus.

FIG. 7 is a diagram illustrating a data structure used in errorcorrection of data read from a media.

FIG. 8 is a diagram for explaining change of access destinationaddresses in the demodu-transfer.

FIG. 9 is a diagram for explaining change of access destinationaddresses at the external code reading for the ECC read request.

FIG. 10 is a diagram illustrating an access state of only the post-stageprocessing section 4 in the prior art information processing apparatus.

FIG. 11 is a block diagram illustrating a configuration of aninformation processing apparatus in which memories are integrated.

FIG. 12 is a diagram illustrating a state where memory accesses arebroken in the prior art information processing apparatus in whichmemories are integrated.

BEST MODE TO EXECUTE THE INVENTION Embodiment 1

An information processing apparatus according to a first embodiment ofthe present invention will be described with reference to the drawings.

FIG. 1 is a block diagram illustrating a configuration of an informationprocessing apparatus 101 according to the first embodiment.

The information processing apparatus 101 according to the firstembodiment processes data accumulated in a media 2, and comprises apre-stage processing section 3 for accessing the media 2, a post-stageprocessing section 4 for performing processing of data read from themedia 2 by the pre-stage processing section 3 and creating data to bewritten into the media 2 by the pre-stage processing section 3, anintegrated memory 5 which can be accessed by the respective processingsections, and an integrated memory control circuit 18 for arbitratingaccess to the integrated memory 5 from the pre-stage processing section3 and the post-stage processing section 4.

The pre-stage processing section 3 is connected to the media 2 throughdata signals 6 a and 6 b, and has functions of either/both reading datafrom the media 2 or/and writing data into the media 2. In order torealize the functions, the pre-stage processing section 3 comprises arequester group 7 and a requester group 8 as factors for generatingplural access requests with respect to the integrated memory 5. Therequester group 7 issues plural access requests through request signals12 a which are provided by the same number as the number of accessrequests. Similarly, the requester group 8 issues plural access requeststhrough request signals 12 b which are provided by the same number asthe number of access requests. Further, the pre-stage processing section3 includes an access request control circuit 22 which outputs apredetermined number of access requests to the integrated memory controlcircuit 18 among plural access requests from the requester group 7 andthe requester group 8. The access request control circuit 22 isconnected to the requester group 7 through request signals 12 a and adata signal 14 a, to the requester group 8 through request signals 12 band a data signal 14 b, and to the integrated memory control circuit 18through request signals 20 and a data signal 21.

The access request control circuit 22 outputs a predetermined number ofaccess requests from among plural access requests from the requestergroup 7 and the requester group 8, to the request signals 20 which areprovided by a predetermined number so that the predetermined number ofaccess requests can be simultaneously output, and includes anarbitration unit 130 which temporarily accumulates the supplied data inthe buffer 131, as having a configuration shown in FIG. 1(b). Thearbitration unit 130 is connected to the requester group 7 throughrequest signals 12 a and the data signal 14 a and to the requester group8 through request signals 12 b and the data signal 14 b. Further, thearbitration unit 130 is connected to the buffer 131 through a datasignal 132 and to the integrated memory control circuit 18 through therequest signals 20 and the data signal 21.

The arbitration unit 130 has a function of judging whether each of theaccess requests from the requester group 7 and the requester group 8 isto be issued to the integrated memory control circuit 18 as a request ofone word length as it is or each of the access requests is to beconverted into a transfer request of consecutive longer transfer lengthsuch as multiple-word lengths and issued so as to temporarily accumulatethe data supplied according to the access requests in the buffer 131(hereinafter, referred to as bursting judgement), and a function ofjudging at what priority among plural stages of priorities an accessrequest is to be issued when the access request is issued to theintegrated memory control circuit 18. The access factor for which accessdestination addresses change with regularity is an access factor whichcan be burst, and therefore the access factor is converted into anaccess request of longer transfer length to be outputted, while theother access factors are access factors which cannot be burst, andtherefore each of the access factors is output as an access request ofone word length as it is. Here, the respective signals of the requestsignals 20 are set to different priorities, respectively, and thearbitration unit 130 outputs an issued access request to a signal forwhich a priority corresponding to a priority for the access request isset. That is, the arbitration unit 130 issues an access requestgenerated by an access factor which cannot be burst, and an accessrequest generated by an access factor which can be burst and for whichtransfer requests are always generated at regular intervals, through arequest-signal of a higher priority among the request signals 20. On theother hand, the arbitration unit 130 issues an access request generatedby an access factor which can be burst and is continuously generatedwith no time interval after a request is accomplished, through a requestsignal of a lower priority among the request signals 20.

Here, in a case where the media 2 is a DVD and the informationprocessing apparatus 101 is an apparatus which reads data recorded onthe DVD and outputs a video signal and an audio signal, the requestergroup 7 comprises three access factors of a CPU request from a centralprocessing unit (not shown) which controls the information processingapparatus 1, a demodu-request for demodulating data read from the media2 and writing the demodulated data into the integrated memory 5, and anECC correction request for correcting error data found in the errorcorrection. In this case, three signals of 12 a 0 to 12 a 2 whichtransmit the respective access requests are provided as request signals12 a, and the CPU request, the demodu-request, and the ECC correctionrequest are input to the arbitration unit 130 in the access requestcontrol circuit 22, through the signal 12 a 0, the signal 12 a 1, andthe signal 12 a 2, respectively.

Further, the requester group 8 comprises three access factors of an ECCread request for performing error correction of data which was writtenaccording to the demodu-request, and an EDC request for checking whetheran error is left on the error-corrected data, and a HOST transferrequest for outputting data which is confirmed as having no error to thedata signal 11 a. In this case, three signals of 12 b 0 to 12 b 2 whichtransmit the respective access requests are provided as request signals12 b, and the ECC read request, the EDC request, and the HOST transferrequest are input to the arbitration unit 130 in the access requestcontrol circuit 22, through the signal 12 b 0, the signal 12 b 1, andthe signal 12 b 2, respectively.

Furthermore, three signals of a first priority request signal 200, asecond priority request signal 201, and a third priority request signal202 in descending order of priority are provided as request signals 20for outputting access requests through signals 12 a 0 to 12 a 2 andsignals 12 b 0 to 12 b 2 to the integrated memory 5. The first priorityrequest signal 200 of the highest priority is occupied by the CPUrequest, the second priority request signal 201 of the highest prioritybut the first priority request signal 200 is shared by thedemodu-request and the ECC correction request, and the third priorityrequest signal 202 of the lowest priority is shared by the ECC readrequest, the EDC request, and the HOST transfer request.

The post-stage processing section 4 is connected to the pre-stageprocessing section 3 through a data signal 11 a and a data signal 11 b,and has functions of either/both performing processing of data which areread from the media 2 by the pre-stage processing section 3 or/andcreating data to be written into the media 2 by the pre-stage processingsection 3. Further, the post-stage processing section 4 includes arequester group 9 as factors for generating plural access requests withrespect to the integrated memory 5. The requester group 9 issues pluralaccess requests through request signals 13 a which are provided by thesame number as the number of access factors, and is connected to theintegrated memory control circuit 18 through the request signals 13 aand a data signal 15 a.

The integrated memory control circuit 18 arbitrates among the accessrequests from the pre-stage processing section 3 (request signals 20)and the access requests from the post-stage processing section (requestsignals 13 a). In a case where the information processing apparatus 101accesses a DVD, the access request of the first priority request signal200 is adapted to have the highest priority, and then the accessrequests of the second priority request signal 201, the access requestsof the request signals 13 a, and the access requests of the thirdpriority request signal 202 are adapted to have the lower priorities inthis order, at the arbitration.

The integrated memory 5 is an SDRAM of 16 bit width. Hereinafter, a casewhere an address of the integrated memory 5 is indicated by a logicaladdress of one word length of 32 bits will be described as an example.

Next, an operation of the information processing apparatus 101constructed as above will be described with taking, as an example, acase where the media 2 is a DVD and the information processing apparatus101 is an apparatus for accessing the DVD.

The arbitration unit 130 in the access request control circuit 22arbitrates among the request signals 12 a output from the requestergroup 7 and the request signals 12 b output from the requester group 8as follows.

That is, when the arbitration unit 13 receives a CPU request (requestsignal 12 a 0), the arbitration unit 130 judges that the request cannotbe burst, and immediately issues an access request of transfer wordlength 1 as an access request requiring a higher priority through thefirst priority request signal 200. In a case where contents of theaccess request are write request, the arbitration unit 130 wait for apermission from the integrated memory control circuit 18 to output dataof the data signal 14 a to the data signal 21, and notifies therequester group 7 of the accomplishment of the access request. In a casewhere contents are read request, the arbitration unit 130 wait for apermission from the integrated memory control circuit 18 to output dataof the data signal 21 to the data signal 14 a, and notifies therequester group 7 of the accomplishment of the access request.

When the arbitration unit 130 receives a demodu-request (request signal12 a 1), the arbitration unit 130 judges that the request is an accessrequest which can be burst. Then, the arbitration unit 130 outputs dataof the media 2, which are supplied through the data signal 14 a, to thedata signal 132 to accumulate the data in the buffer 131, and notifiesthe requester group 7 of the accomplishment of the access request. Thisoperation will be repeated, and when a requested transfer length of thedemodu-request is X, data of word length X are accumulated in the buffer130. When data of word length X are accumulated in the buffer 131, thearbitration unit 130 issues a write request for word length X to thesecond priority request signal 201. Here, the demodu-request is anaccess factor which generates an access request at regular timeintervals, and thereby the demodu-request is output to the secondpriority request signal 201 as an access request of a higher priority.However, in a case where an access request has already been issued tothe second priority request signal 201 by the ECC correction request andthe request has not been accomplished, the arbitration unit 130 causesthe demodu-request to wait until the ECC correction request isaccomplished.

When the demodu-request is output to the second priority request signal201, the arbitration unit 130 waits for a permission from the integratedmemory control circuit 18 to consecutively read data of word length Xaccumulated in the buffer 131 through the data signal 132, and outputsthe read signal to the data signal 21. As described above, thedemodu-request is an access request generated at regular time intervals.For example, when the DVD operates at double speed, the data to bewritten according to the demodu-request are generated at a rate ofapproximately one word length per 1.25 μs. Therefore, in a case wheredata of X word length are accumulated and then an access request to theintegrated memory control circuit 18 is issued, the interval at whichthe access request is issued is approximately 1.25 Xμs.

When the arbitration unit 130 receives an ECC correction request(request signal 12 a 2), the arbitration unit 130 judges that therequest is an access request which cannot be burst, and immediatelyissues an access request of transfer word length 1 as an access requestrequiring a higher priority through the second priority request signal201. Then, the arbitration unit 130 waits for a permission from theintegrated memory control circuit 18 to output the correction data tothe data signal 21 and notifies the requester group 7 of theaccomplishment of the request. However, in a case where when the ECCcorrection request is input to the arbitration unit 130, an accessrequest has already been issued to the second priority request signal201 by the demodu-request and the request has not been accomplished, thearbitration unit 130 causes the ECC correction request to wait until thedemodu-request is accomplished.

When the arbitration unit 130 receives an ECC read request (requestsignal 12 b 0), the arbitration unit 130 judges that the request is anaccess request which can be burst, and issues an access request of kword length as a transfer length through the third priority requestsignal 202 as an access request for which a lower priority is to be set.However, in a case where an access request has already been issued tothe third priority request signal 202 by the EDC request or the HOSTtransfer request, and the request has not been accomplished, thearbitration unit 130 causes the ECC read request to wait until therequest is accomplished.

After the ECC read request is output, the arbitration unit 130 waits fora permission from the integrated memory control circuit 18 toconsecutively output data of k word length from the data signal 21 tothe data signal 132 and write the data into the buffer 131. Then, datacorresponding to the access destination address are output to the datasignal 14 b and the requester group 8 is notified of the accomplishmentof the request.

Here, realization of the ECC read request will be described in moredetail.

In the case of external code reading, when an address requested to beaccessed is pd which is a head of the data area D1, the data reading upto the address pd+ko which is ahead of the address pd by ko is required.That is, the transfer length k is given as k=ko+1. These read data ofaddresses pd+1, pd+2, . . . , pd+ko are data corresponding to n timeslater, 2n times later, . . . , (ko×n) times later ECC read requests,respectively. Therefore, the data accumulated in the buffer may betransferred for n times later, 2n times later, . . . , (ko×n) timeslater ECC read requests, and accesses to the integrated memory 5 areunnecessary. In a method in which data of one word length is read fromthe integrated memory 5 every time an access request is generated, theperformance of the integrated memory is degraded. However, when previousreading is performed by (ko+1) word length reading as described above,the access can be converted into consecutive access for (ko+1) wordlength. On the other hand, in the case of internal code reading, when anaddress pd is required to be accessed, data reading up to an addresswhich is ahead of the address pd by a natural number ki is required.That is, transfer length k is given as k=ki+1. Therefore, in this case,the access can be converted into consecutive access for ki+1 wordlength.

On the other hand, in a case where the data of the address required bythe ECC read request (request signal 12 b 0) is read by the previousaccess request and have already been included in the buffer 131, thearbitration unit 130 does not issue an access request to the thirdpriority request signal 202, and outputs the corresponding data in thebuffer 131 to the data signal 14 b through the data signal 132, andreports the accomplishment of the access request.

When the arbitration unit 130 receives an EDC request (request signal 12b 1), the arbitration unit 130 issues an access request through thethird priority request signal 202. However, in a case where an accessrequest has already been issued to the third priority request signal 202by an ECC read request or a HOST transfer request, and the request hasnot been accomplished, the arbitration unit 130 causes the EDC requestto wait until the request is accomplished and no ECC read request iswaiting.

Here, when an access destination address is p and a requested transferlength is k1+1, the EDC request requires that data of addresses p top+k1 be read. The arbitration unit 130 waits for a permission from theintegrated memory control circuit 18 to consecutively output the data ofk1+1 word length through the data signal 21 to the data signal 132,writes the data into the buffer 131, outputs data corresponding toaddress p to the data signal 14 b, and notifies the requester group 8 ofthe accomplishment of the request.

On the other hand, in a case where data of the address requested by theEDC request are read by the previous access request and have alreadybeen included in the buffer 131, the arbitration unit 130 does not issuean access request to the third priority request signal 202, outputs thecorresponding data in the buffer 131 to the data signal 14 b through thedata signal 132, and reports the accomplishment of the access request.

When the arbitration unit 130 receives a HOST transfer request (requestsignal 12 b 2), the arbitration unit 130 issues an access requestthrough the third priority request signal 202. However, in a case wherean access request has already been issued to the third priority requestsignal 202 by an ECC read request or an EDC request, and the request hasnot been accomplished, the arbitration unit 130 causes the HOST transferrequest to wait until the request is accomplished and there are nowaiting ECC read request and EDC request.

Here, when an access destination address is p and a requested transferlength is k2+1, the arbitration unit 130 requests that data of addressesp to p+k2 be read. Then, the arbitration unit 130 waits for a permissionfrom the integrated memory control circuit 18 to consecutively outputdata of K2+1 word length from the data signal 21 to the data signal 132,writes the data into the buffer 131, outputs data corresponding toaddress p to the data signal 14 b, and notifies the requester group 8 ofthe accomplishment of the request.

On the other hand, in a case where data of the address p requested bythe HOST transfer request are read by the previous access request andhave already been included in the buffer 131, the arbitration unit 130does not issue an access request to the third priority request signal202, outputs the corresponding data in the buffer 131 to the data signal14 b through the data signal 132, and reports the accomplishment of theaccess request.

Next, a description concerning that the access request control circuit22 arbitrates among access factors of the pre-stage processing section 3as described above, thereby avoiding the breakage of memory access ofthe pre-stage processing section 3 and the breakage of memory access ofthe post-stage processing section 4, will be given.

The worst value of the occupied bandwidth inclusive of overhead for thepre-stage processing section 3 is given by the following formula usingthe respective values of a requested transfer length of the respectiveaccess factors, X, ko, ki, k1, and k2.18.6+16.1(1/X+1/(ko+1)+1/(ki+1))+2.45+13.9(1/(k1+1)+1·(k2+1))

Using this formula, X, ko, ki, k1, and k2 are determined so that thewhole bandwidth of the information processing apparatus 1 is within thebandwidth of the integrated memory 5, thereby avoiding breakage ofbandwidth substantially.

Subsequently, as to the respective access factors of the pre-stageprocessing section 3, it is discussed whether the memory access can benormally accomplished or not.

The CPU request has the highest priority of all the access requests, andexclusively occupies the first priority request signal 200. Therefore,even under the worst condition, its waiting time is the shortest of allthe access factors, thereby meeting the requirements of quick responseto the memory access.

The demodu-request shares, with an ECC correction request, the secondpriority request signal 201 having the highest priority but the firstpriority request signal 200. Therefore, the demodu-request is not causedto wait by access factors other than a CPU request and an ECC request,thereby obtaining quick response.

The ECC correction request shares the second priority request signal 201with a demodu-request. The ECC correction request is issued to theintegrated memory control circuit 18 as a single-shot write request ofone word length. In a case where the ECC correction request, whichcannot be burst, is issued using the third priority request signal 202,the problem described below occurs. Further, using the first priorityrequest signal 200 causes the waiting time to be generated for the CPUrequest, and it is not desirable. Therefore, the second priority requestsignal 201 is used for the ECC correction request. Then, the ECCcorrection request is not caused to wait by the access factors otherthan a CPU request and a demodu-request, thereby avoiding breakage ofprocessing due to delay in memory access.

The ECC read request, the EDC request, and the HOST transfer requestshare the third priority request signal 202 having a priority lower thanthe request signals 13 a from the post-stage processing section 4. Theseaccess factors can be burst, and therefore these access factors areissued as access requests of longer requested transfer length. Further,for these access factors, the access requests are issued independentlyfrom each other in progress of processing, and the access requests canbe continuously issued as shown in FIG. 2. FIG. 2 shows access states ofthe ECC read request, the EDC request and the HOST transfer request, anda location where “req” is described designates a time at which an accessrequest is issued, an area where “access” is described designates a timeperiod during which data transfer is being performed, and an area where“wait” is described designates a waiting time. For the ECC read request,the EDC request, and the HOST transfer request, access requests areissued independently from each other in progress of processing as shownin FIG. 2, and therefore access can be intensively accomplished. Thus,it is a sufficient condition for completing the ECC read request, theEDC request and the HOST transfer request without being broken thatthere is a room in the bandwidth.

If X, ko, ki, k1, and k2 are properly defined in the above-describedformula and thereby the whole bandwidth of the information processingapparatus 101 falls within the bandwidth of the integrated memory 5 witha room of approximately 10%, even when the third priority request signal202 has the lowest priority of all the access factors, breakage ofprocessing due to delay in memory access can be avoided. On the otherhand, when access factors of the post-stage processing section 4 forwhich the access requests are arbitrated so as to have a priority lowerthan the third priority request signal 202 is assumed, the operationwill be in a state similar to that in the case shown in FIG. 12, andthere is a possibility that for the access factors for which the accessrequests are arbitrated so as to have a priority lower than the thirdpriority request signal 202, the access requests cannot be accomplisheduntil an ECC read request, an EDC request, and a HOST transfer requestare all accomplished. Therefore, it is necessary that the third priorityrequest signal 202 should have the lowest priority of all the accessfactors which are arbitrated by the arbitration unit 130. Assuming thatthe third priority request signal 202 is used for the ECC correctionrequest, the following matter would occur because the ECC correctionrequest is a single-shot write request in units of one word length. Forexample, in a case where the request of the third priority requestsignal 202 is accepted 10 times, the transfer of 10 bytes in total isonly accomplished for the ECC correction request, while transfer of 160word length or more is possible for the ECC read request, the EDCrequest, and the HOST transfer request. That is, the frequency withwhich the third priority request signal 202 may be transferred islittle, and when ECC correction request is transferred through the thirdpriority request signal 202, there is a possibility that the ECC readrequest, the EDC request, and the HOST transfer request may be delayed.Therefore, it is appropriate that the third priority request signal 202is not used for the ECC correction request.

Further, as for the information processing apparatus 101, reviewing theaccess states for the access factors of the post-stage processingsection 4 in the worst condition described above, the states are asshown in FIG. 3. FIG. 3 shows access states for an ECC read request, anEDC request, a HOST transfer request, and access factors A to C of thepost-stage processing section 4. It is assumed that the ECC read requestis accepted, and thereafter the access requests for the access factorsA, B, and C of the post-stage processing section 4 are issued at thesame timing, and a demodu-request and an ECC correction request areissued when the access request for access factor A is being executed.The demodu-request is converted by being burst to issue a request foroccupying the integrated memory 5 for 10N cycles inclusive of overhead.Further, with this bursting, an interval at which an access request tothe integrated memory control circuit 18 for the demodu-request isissued, is 700N cycles.

For an ECC correction request, an access request of one word length isissued up to 16 times. An access to the integrated memory 5 for one ECCcorrection request takes only N cycles, thereby completing the access ina short time. Therefore, even when an access to the integrated memory 5for the ECC correction request is performed after the access factors Aand B are completed, the subsequent access requests are not issued forthe access factors A and B, thereby also accepting the access requestfor the access factor C.

As described above, since a transfer length of the ECC correctionrequest is shorter, even when an extremely high priority is set for theECC correction request, access factors of lower priorities are notaffected. An ECC read request, an EDC request, and a HOST transferrequest have the lowest priority, and thereby the access requests arenot accepted in a time period during which accesses of the post-stageprocessing section 4 are frequently performed as shown in FIG. 3, andthe access requests of the post-stage processing section 4 are notprevented. Consequently, even under the worst condition, a micro memoryaccess breakage of the post-stage processing section 4 is avoided.

As described above, in the information processing apparatus 101according to the first embodiment, the pre-stage processing section 3 inwhich the access request control circuit 22 arbitrates among pluralaccess requests with respect to the integrated memory 5 and which issuesa predetermined number of access requests, the post-stage processingsection 4 which issues plural access requests with respect to theintegrated memory 5, and the integrated memory control circuit 18 whicharbitrates among access requests from the pre-stage processing section 3and the post-stage processing section 4 and outputs any of the accessrequests to the integrated memory 5, are provided, and the accessrequest control circuit 22 and the integrated memory control circuit 18are adapted to perform arbitration on the basis of periodicities of therespective access factors and regularity of the access destinationaddress. Therefore, the pre-stage processing section 3 and thepost-stage processing section 4, which have the different data transferrates, can share the integrated memory 5 without breaking the memoryaccess. With this, a low-speed memory accessed by the pre-stageprocessing section 3 can be dispensed with, and moreover the pre-stageprocessing section 3 and the post-stage processing section 4 can beformed in a single semiconductor integrated circuit, thereby reducingthe number of components and a footprint and reducing production cost.

Then, while in this embodiment two step arbitrations by the integratedmemory control circuit 18 and the access request control circuit 22 isperformed for the access requests of the pre-stage processing section 3,the integrated memory control circuit 18 may arbitrate the accessrequests of the pre-stage processing section 3. For example, theintegrated memory control circuit 18 may be provided with channelscorresponding to the number of all the access factors of the pre-stageprocessing section 3, and the buffer 131 included in the access requestcontrol circuit 22, and arbitrate among access requests from thepre-stage processing section 3 and the post-stage processing section 4based on the same reference as that of the access request controlcircuit 22, that is, whether the access request can be burst and whetherthe access request is consecutively issued or periodically issued. Inthis case, the integrated memory control circuit 18 is dispensed with,thereby reducing a circuit scale of the information processingapparatus.

Embodiment 2

An information processing apparatus according to a second embodiment ofthe present invention will be described with reference to the drawings.The second embodiment is an example in which an additional constituentis added to the information processing apparatus 101 according to thefirst embodiment.

FIG. 4 is a block diagram illustrating a configuration of theinformation processing apparatus 102 according to the second embodiment.Then, in FIG. 4, the same reference numerals as those shown in FIG. 1denote the same or corresponding portions, and the detailed descriptionwill be omitted.

In FIG. 4, reference numeral 240 denotes an access frequencynotification signal which notifies an arbitration unit 230 in the accessrequest control circuit 22 of the pre-stage processing section 3 whetherdata are being decoded by the post-stage processing section 4 or not.

Data supplied from the pre-stage processing section 3 are not alwaysbeing decoded by the post-stage processing section 4 when theinformation processing apparatus 1 is in operation, and a time periodduring which no decoding is performed occurs. For example, when thesupplied data are compressed image data, a time period during which nodecoding is performed occurs every one frame as a unit of imageprocessing. Hereinafter, this time period is referred to as a blankperiod.

Next, an operation of the information processing apparatus 102constructed as above will be described.

The post-stage processing section 4 notifies the access request controlcircuit 22 of the information as to whether the post-stage processingsection 4 is in a blank period or not. The access frequency notificationsignal 240 is a signal which becomes HI during the blank period andbecomes LOW except during the blank period.

In the access request control circuit 22, the arbitration unit 230refers to the access frequency notification signal 240 to obtain theinformation as to whether the post-stage processing section 4 is in ablank period or not, and controls issuance of access requests.

That is, when the post-stage processing section 4 is not in a blankperiod, the arbitration unit 230 issues access requests to theintegrated memory control circuit 18 at regular time intervals. On theother hand, when the post-stage processing section 4 is in a blankperiod, the arbitration unit 230 issues access requests to theintegrated memory control circuit 18 with no time interval.

As described above, in the information processing apparatus 102according to the second embodiment, an access frequency notificationsignal 240 indicating whether the post-stage processing section 4 is ina blank period or not is input to the arbitration unit 230, and thearbitration unit 230 issues access requests to the integrated memorycontrol circuit 18 at regular time intervals when the post-stageprocessing section 4 is not in a blank period, while the arbitrationunit 230 issues access requests to the integrated memory control circuit18 with no time interval when the post-stage processing section 4 is ina blank period, and thereby the access requests from the pre-stageprocessing section 3 do not cause the processing of the post-stageprocessing section 4 to be delayed. At this time, occurrence of waitingtimes caused by the access requests from the post-stage processingsection 4 can be avoided for an EDC request, a HOST transfer request,and the like, thereby intensively accomplishing access requests.

Further, even if an EDC request, a HOST transfer request, and an ECCread request are not always issued at a lower priority, the accessrequests of the requester group 9 cannot be prevented by the operationof the arbitration unit 230. Therefore, a configuration in which thethird priority request signal 202 of the first embodiment is deleted ispossible. In this case, the circuit scales of the integrated memorycontrol circuit 18 and the access request control circuit 22 can bereduced.

Embodiment 3

An information processing apparatus according to a third embodiment ofthe present invention will be described with reference to the drawings.The third embodiment is an example of a modification of the informationprocessing apparatus 101 according to the first embodiment, which isobtained by adding an additional element such as a software to theapparatus 101.

FIG. 5 is a block diagram illustrating a configuration of theinformation processing apparatus 103 according to the third embodiment.Then, in FIG. 5, the same reference numerals as those shown in FIG. 1denote the same or corresponding portions, and the detailed descriptionwill be omitted.

In FIG. 5, reference numeral 351 denotes an access frequency register inwhich a setting as to whether the post-stage processing section 4 is ina blank period or not is performed, reference numeral 352 denotes acontrol register group comprising plural registers in which modes areset, respectively, and reference numeral 350 denotes a CPU which sets amode in any of the registers in the control register group 352 on thebasis of the setting value of the access frequency notification register351. Further, the CPU 350 is connected to the access frequencynotification register 351 through an access frequency notificationsignal 357, and to the control register group 352 through an addresssignal 355 and a data signal 356. The control register group 352 isconnected to the requester group 7 through a data signal 353 and to therequester group 8 through a data signal 354.

The CPU 350 selects a specific register in the control register group352 through the address signal 355, and can freely set a value in theselected register through the data signal 356.

The control register group 352 is provided with the registers by thesame number as the number of access factors of the requester group 7 andthe requester group 8, and as for the respective access factors of therequester group 7 and the requester group 8, a value of thecorresponding register in the control register group 352 can be referredto through the data signal 353 or the data signal 354.

Here, in a case where the setting values of the control register group352 indicate operation modes for the respective request factors, the CPU350 can set the operation modes for the respective access factors of therequester group 7 and the requester group 8 through the control registergroup 352.

Hereinafter, the operation modes for the respective access factors willbe described.

The access factor is the same between the ECC read request and the ECCcorrection request, and the access factor has two modes of a normal ECCmode for performing error correction processing at the highest possiblespeed and an ECC stop mode in which no error correction processing isperformed. In the normal ECC mode, when an ECC read request isaccomplished, the subsequent ECC read request is generated with NoWait.On the other hand, an ECC read request and an ECC correction request arenot generated in the ECC stop mode.

The access factor of the EDC request has two modes of a normal EDC modefor performing error detection processing at the highest possible speedand an EDC stop mode in which no error correction processing isperformed. In the normal EDC mode, when a request is accomplished forthe access factor of the EDC request, the subsequent EDC request isgenerated with NoWait. On the other hand, no EDC request is generated inthe EDC stop mode.

The access factor of the HOST transfer request has two modes of a normalHOST transfer mode for performing the HOST transfer processing at thehighest possible speed and a HOST transfer stop mode in which no HOSTtransfer processing is performed. In the normal HOST transfer mode, whena HOST transfer request is accomplished, the subsequent HOST transferrequest is generated with NoWait. On the other hand, no HOST transferrequest is generated in the HOST transfer stop mode.

Next, an operation of the information processing apparatus 102constructed as above will be described.

The post-stage processing section 4 sets 1 in the access frequencynotification register 351 when the post-stage processing section 4 is ina blank period and otherwise it sets 0.

The CPU 350 detects a setting value in the access frequency notificationregister 351 using the access frequency notification signal 240. Whenthe post-stage processing section 4 is in a blank period, the CPU 350sets values in the control register group 352 through the address signal355 and the data signal 356, thereby to set the operation mode of theaccess factor of the ECC read request, the operation mode of the accessfactor of the EDC request, and the operation mode of the access factorof the HOST transfer request, to the normal ECC mode, the normal EDCmode, and the normal HOST transfer mode, respectively.

On the other hand, when the post-stage processing section 4 is not in ablank period, the CPU 350 sets values in the control register group 352through the address signal 355 and the data signal 356 so that theoperation mode of the access factor of the ECC read request isperiodically and alternately changed to the normal ECC mode and the ECCstop mode, the operation mode of the access factor of the EDC request isperiodically and alternately changed to the normal EDC mode and the EDCstop mode, the operation mode of the access factor of the HOST transferrequest is periodically changed to the normal HOST transfer mode or theHOST transfer stop mode.

Alternatively, when the post-stage processing section 4 is not in ablank period, the CPU 350 may set the access factor of the ECC readrequest, the access factor of the EDC request, and the access factor ofthe HOST transfer request mode, to the ECC stop mode, the EDC stop mode,and the HOST transfer stop mode, respectively.

As described above, the information processing apparatus 102 accordingto the third embodiment comprises the access frequency register 351 inwhich setting as to whether the post-stage processing section 4 is in ablank period or not is performed, the control register group 352comprising plural registers in which modes are set, and the CPU 350 forsetting a mode in any of the registers in the control register group 352on the basis of the setting value in the access frequency notificationregister 351. Therefore, when the post-stage processing section 4 is notin a blank period, the operation mode of the access factor of the ECCread request is periodically and alternately changed to the normal ECCmode and the ECC stop mode, the operation mode of the access factor ofthe EDC request is periodically and alternately changed to the normalEDC mode and the EDC stop mode, and the operation mode of the accessfactor of the HOST transfer request is periodically changed to thenormal HOST transfer mode or the HOST transfer stop mode, on the basisof the setting in the control register group 352. Thereby, the accessrequests from the pre-stage processing section 3 do not cause theprocessing of the post-stage processing section 4 performed during thetime periods other than a blank period to be delayed. Further, when thepost-stage processing section 4 is in a blank period, no access requestof the requester group 9 is generated, and therefore access requests ofthe requester group 8 are generated with NoWait, thereby intensivelyaccomplishing the access requests of the requester group 8.

Further, even if the respective access requests of the ECC read request,the EDC request, and the HOST transfer request are not always issued ata lower priority, access requests of the requester group 9 are notprevented by the operation of the arbitration unit 130. Therefore, aconfiguration in which the third priority request signal 202 of thefirst embodiment is deleted is possible. In this case, the circuitscales of the integrated memory control circuit 18 and the accessrequest control circuit 22 can be reduced.

APPLICABILITY IN INDUSTRY

An information processing apparatus of the present invention is usefulbecause memory accesses to one storage unit from plural processingsections are performed without breaking the memory accesses, therebyreducing the number of components and production cost.

1-9. (canceled)
 10. An information processing apparatus comprising: astorage unit for storing data; a first data processing section forissuing plural access requests by a first access request generation unitfor generating access requests of a higher priority and a second accessrequest generation unit for generating access requests having a lowerpriority and consecutiveness in access destination address, andaccessing the storage unit; a second data processing section for issuingaccess requests and accessing the storage unit; an access requestcontroller having an arbitration unit for adding the highest priority tothe access requests from the first access request generation unit, andadding a priority lower than that of the access requests from the seconddata processing section to the access requests from the second accessrequest generation unit, the access request controller arbitrating amongplural access requests from the first data processing section to outputa predetermined number of access requests; and an access arbitrationunit for arbitrating among the access requests from the access requestcontroller and the access requests from the second data processingsection.
 11. The information processing apparatus as defined in claim10, wherein the access request controller comprises a buffer foraccumulating data, and when an access request from the first dataprocessing section is a write request with respect to the storage unit,the arbitration unit judges whether the arbitration unit issues anaccess request for writing a data amount which is requested by the writerequest, or accumulates a specified amount of data to be written, in thebuffer, and thereafter converts the request into an access request forintensively writing the accumulated data to issue the converted accessrequest.
 12. The information processing apparatus as defined in claim10, wherein the access request controller comprises a buffer foraccumulating data, and when an access request from the first dataprocessing section is a read request with respect to the storage unit,the arbitration unit judges whether the arbitration unit issues anaccess request for reading data of an amount requested by the readrequest, or converts the request into an access request for intensivelyand previously reading more data than the requested amount by aspecified amount and accumulating the read data in the buffer to issuethe converted access request, or reads the data accumulated in thebuffer without issuing an access request.
 13. The information processingapparatus as defined in claim 10, wherein the first data processingsection issues access requests which are periodically generated atregular time intervals, from the first access request generation unit,and issues access requests which are consecutively generated with notime interval after an access request is accomplished, from the secondaccess request generation unit.
 14. The information processing apparatusas defined in claim 10, wherein the first data processing sectioncomprises: a demodulating and writing means for demodulating datarecorded in a storage medium which can be accessed by the first dataprocessing section and writing the demodulated data into the storageunit; an error correction means for reading data written in the storageunit and writing error-corrected data obtained by error-correcting theread data into the storage unit; an error detection means for readingthe data which have been error-corrected from the storage unit andchecking the data for error; and a reading means for reading data whichis confirmed to have no error by the error detection means, from thestorage unit, and outputting the read data to the second data processingsection, and when an access request from the first data processingsection is generated by the demodulating and writing means, thearbitration unit sets a priority of an access request to be issued tothe access arbitration unit higher than a priority of access requestsfrom the second data processing section, and when an access request ofthe first data processing section is generated by any of the errorcorrection means, the error detection means, and the reading means, thearbitration unit sets a priority of an access request to be issued tothe access arbitration unit lower than a priority of access requestsfrom the second data processing section.
 15. The information processingapparatus as defined in claim 10, wherein the second data processingsection or the access arbitration unit comprises an access frequencydetection unit for detecting a time period during which occurrencefrequency of access to the storage unit from the second data processingsection is low, and notifying the access request controller of the timeperiod, and the access request controller suppresses issuance of accessrequests except in the time period and promotes issuance of accessrequests in the time period on the basis of the notification from theaccess frequency detection unit.
 16. The information processingapparatus as defined in claim 10 wherein the first data processingsection comprises: an error correction means for reading data written inthe storage unit and writing error-corrected data obtained byerror-correcting the read data into the storage unit; and a readingmeans for reading data which is confirmed to have no error by the errordetection means, from the storage unit, and outputting the read data tothe second data processing section, and the second data processingsection or the access arbitration unit comprises an access frequencydetection unit for detecting a start and an end of a time period duringwhich occurrence frequency of access to the storage unit from the seconddata processing section is low, and notifying the access requestcontroller of the start and the end, and the first data processingsection operates the error correction means and the reading means whenthe start of the time period is detected by the access frequencydetection unit, and the first data processing section delays or stopsthe operations of the error correction means and the reading means whenthe end of the time period is detected.
 17. The information processingapparatus as defined in claim 11, wherein the first data processingsection comprises: a demodulating and writing means for demodulatingdata recorded in a storage medium which can be accessed by the firstdata processing section and writing the demodulated data into thestorage unit; an error correction means for reading data written in thestorage unit and writing error-corrected data obtained byerror-correcting the read data into the storage unit; an error detectionmeans for reading the data which have been error-corrected from thestorage unit and checking the data for error; and a reading means forreading data which is confirmed to have no error by the error detectionmeans, from the storage unit, and outputting the read data to the seconddata processing section, and when an access request from the first dataprocessing section is generated by the demodulating and writing means,the arbitration unit sets a priority of an access request to be issuedto the access arbitration unit higher than a priority of access requestsfrom the second data processing section, and when an access request ofthe first data processing section is generated by any of the errorcorrection means, the error detection means, and the reading means, thearbitration unit sets a priority of an access request to be issued tothe access arbitration unit lower than a priority of access requestsfrom the second data processing section.
 18. The information processingapparatus as defined in claim 12, wherein the first data processingsection comprises: a demodulating and writing means for demodulatingdata recorded in a storage medium which can be accessed by the firstdata processing section and writing the demodulated data into thestorage unit; an error correction means for reading data written in thestorage unit and writing error-corrected data obtained byerror-correcting the read data into the storage unit; an error detectionmeans for reading the data which have been error-corrected from thestorage unit and checking the data for error; and a reading means forreading data which is confirmed to have no error by the error detectionmeans, from the storage unit, and outputting the read data to the seconddata processing section, and when an access request from the first dataprocessing section is generated by the demodulating and writing means,the arbitration unit sets a priority of an access request to be issuedto the access arbitration unit higher than a priority of access requestsfrom the second data processing section, and when an access request ofthe first data processing section is generated by any of the errorcorrection means, the error detection means, and the reading means, thearbitration unit sets a priority of an access request to be issued tothe access arbitration unit lower than a priority of access requestsfrom the second data processing section.
 19. The information processingapparatus as defined in claim 13, wherein the first data processingsection comprises: a demodulating and writing means for demodulatingdata recorded in a storage medium which can be accessed by the firstdata processing section and writing the demodulated data into thestorage unit; an error correction means for reading data written in thestorage unit and writing error-corrected data obtained byerror-correcting the read data into the storage unit; an error detectionmeans for reading the data which have been error-corrected from thestorage unit and checking the data for error; and a reading means forreading data which is confirmed to have no error by the error detectionmeans, from the storage unit, and outputting the read data to the seconddata processing section, and when an access request from the first dataprocessing section is generated by the demodulating and writing means,the arbitration unit sets a priority of an access request to be issuedto the access arbitration unit higher than a priority of access requestsfrom the second data processing section, and when an access request ofthe first data processing section is generated by any of the errorcorrection means, the error detection means, and the reading means, thearbitration unit sets a priority of an access request to be issued tothe access arbitration unit lower than a priority of access requestsfrom the second data processing section.